1. Field of the Invention
The present invention relates to data transfer operations in a computer system and more specifically, to direct memory access operations in a computer system.
2. Art Background
In a computer system with multiple data processing devices, data transfers occur not only between one device and another, but also between one device and a plurality of other devices in a time-multiplexing fashion to achieve system efficiency. For example, a central processing unit ("CPU") may transfer data to a network device while time-multiplexing data transfer activities with other devices to fully utilize the CPU. Because data transfer rates from various devices may be different, buffers are sometimes implemented as an intermediary between each device and the CPU to optimize data transfer rates of multiple devices. With buffers, data can be temporarily stored until the transfer resource is available or when the transfer destination is free. Implementing a buffer for each device creates a problem for an integrated circuit when there are more and more devices interacting with the CPU, as the more sophisticated systems often require. In an integrated circuit, the die-size limitation simply does not permit more and more buffers and their associated decode logic to be added.
The problem can be illustrated by direct memory access operations transferring data in multiple channels in a computer system. Direct memory access ("DMA") operation is a technique used for computer input/output ("I/O") operations when large volumes of data are to be moved. DMA typically involves an additional module on the system bus. DMA module 100 such as shown in FIG. 1, is capable of emulating the CPU (not shown) and of taking over control of the system bus from the CPU. A DMA operation works as follows: when the CPU wishes to read or write a block of data, it issues a command to DMA module 100. The command includes information regarding whether a read 101 or write 102 is requested, the address 103 of the I/O device involved, the starting location in memory to read from or write to, and the number 105 of words to be read or written. The CPU then continues with other tasks because it has delegated this I/O operation to the DMA module, and the module will take care of the task. The DMA module thus transfers the entire block of data, one word at a time, directly to or from memory, without going through the CPU. When the transfer is completed, the DMA module sends an interrupt signal 110 to the CPU. As such, the CPU only needs to get involved at the beginning and end of the transfer.
The DMA module needs to take control of the bus in order to transfer data to and from memory. For this purpose, the DMA module must use the bus only when the CPU does not need it, or the DMA module must force the CPU to temporarily suspend its operation. Since the only function this DMA module performs is data transfer, the transfer sequence can be hard-wired into the module circuit. By fetching instructions at a much higher level, the use of band-width can be minimized. Since the DMA module has the capability of generating the address and control signals required by the bus, the DMA module is capable of performing I/O operations at full memory speed.
In today's efficient computer systems, DMA operations must also accommodate multiple-channel data transfers with a variety of devices. To facilitate the data transfers, an independent buffer is allocated to a DMA channel. However, as the number of DMA channels increases for more sophisticated operations, the "one-buffer-per-channel" approach becomes less desirable, if not totally impractical. Further, although a single buffer, such as a first-in, first-out ("FIFO") buffer, may serve as an intermediary for the multiple-channel DMA operations, the FIFO still experiences the problem of bottlenecking when one channel needing all the data right away is blocked by another channel's data. Also, as data are transferred into the FIFO, the FIFO is bound to become full, thus forcing transfers to a stop until some data in the FIFO are read out. For the above reasons, the FIFO's in the prior art multiple-channel transfers cannot achieve high band-width and continuous operations.
As will be described in the following, the present invention discloses a method and apparatus for transferring data through multiple DMA channels by interleaving the transfer sequences from different channels to achieve high band-width and efficient resource utilization. Also disclosed is a circuit architecture to be most advantageously used in conjunction with supporting multiple-channel DMA transfers to maximize band-width and system efficiency.